Gecko [ naturenectar.co.uk ]

Name	Size	Permission	Date
android	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
byteorder	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
caif	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
can	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
cifs	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
dvb	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
genwqe	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
hdlc	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
hsi	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
iio	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
isdn	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
misc	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
mmc	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
netfilter	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
netfilter_arp	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
netfilter_bridge	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
netfilter_ipv4	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
netfilter_ipv6	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
nfsd	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
raid	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
sched	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
spi	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
sunrpc	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
surface_aggregator	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
tc_act	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
tc_ematch	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
usb	[ DIR ]	drwxr-xr-x	2025-09-09 19:29
a.out.h	6.73 KB	-rw-r--r--	2025-09-04 09:37
acct.h	3.82 KB	-rw-r--r--	2025-09-04 09:37
acrn.h	16.29 KB	-rw-r--r--	2025-09-04 09:37
adb.h	1.11 KB	-rw-r--r--	2025-09-04 09:37
adfs_fs.h	993 B	-rw-r--r--	2025-09-04 09:37
affs_hardblocks.h	1.54 KB	-rw-r--r--	2025-09-04 09:37
agpgart.h	3.85 KB	-rw-r--r--	2025-09-04 09:37
aio_abi.h	3.32 KB	-rw-r--r--	2025-09-04 09:37
am437x-vpfe.h	3.59 KB	-rw-r--r--	2025-09-04 09:37
apm_bios.h	3.6 KB	-rw-r--r--	2025-09-04 09:37
arcfb.h	213 B	-rw-r--r--	2025-09-04 09:37
arm_sdei.h	2.69 KB	-rw-r--r--	2025-09-04 09:37
aspeed-lpc-ctrl.h	1.74 KB	-rw-r--r--	2025-09-04 09:37
aspeed-p2a-ctrl.h	1.86 KB	-rw-r--r--	2025-09-04 09:37
atalk.h	1023 B	-rw-r--r--	2025-09-04 09:37
atm.h	7.7 KB	-rw-r--r--	2025-09-04 09:37
atm_eni.h	648 B	-rw-r--r--	2025-09-04 09:37
atm_he.h	406 B	-rw-r--r--	2025-09-04 09:37
atm_idt77105.h	955 B	-rw-r--r--	2025-09-04 09:37
atm_nicstar.h	1.25 KB	-rw-r--r--	2025-09-04 09:37
atm_tcp.h	1.58 KB	-rw-r--r--	2025-09-04 09:37
atm_zatm.h	1.5 KB	-rw-r--r--	2025-09-04 09:37
atmapi.h	952 B	-rw-r--r--	2025-09-04 09:37
atmarp.h	1.27 KB	-rw-r--r--	2025-09-04 09:37
atmbr2684.h	3.19 KB	-rw-r--r--	2025-09-04 09:37
atmclip.h	576 B	-rw-r--r--	2025-09-04 09:37
atmdev.h	7.5 KB	-rw-r--r--	2025-09-04 09:37
atmioc.h	1.61 KB	-rw-r--r--	2025-09-04 09:37
atmlec.h	2.33 KB	-rw-r--r--	2025-09-04 09:37
atmmpc.h	4.13 KB	-rw-r--r--	2025-09-04 09:37
atmppp.h	639 B	-rw-r--r--	2025-09-04 09:37
atmsap.h	4.85 KB	-rw-r--r--	2025-09-04 09:37
atmsvc.h	1.81 KB	-rw-r--r--	2025-09-04 09:37
audit.h	21.06 KB	-rw-r--r--	2025-09-04 09:37
auto_dev-ioctl.h	4.87 KB	-rw-r--r--	2025-09-04 09:37
auto_fs.h	6.28 KB	-rw-r--r--	2025-09-04 09:37
auto_fs4.h	451 B	-rw-r--r--	2025-09-04 09:37
auxvec.h	1.56 KB	-rw-r--r--	2025-09-04 09:37
ax25.h	2.76 KB	-rw-r--r--	2025-09-04 09:37
batadv_packet.h	19.87 KB	-rw-r--r--	2025-09-04 09:37
batman_adv.h	16.49 KB	-rw-r--r--	2025-09-04 09:37
baycom.h	883 B	-rw-r--r--	2025-09-04 09:37
bcm933xx_hcs.h	419 B	-rw-r--r--	2025-09-04 09:37
bfs_fs.h	1.86 KB	-rw-r--r--	2025-09-04 09:37
binfmts.h	776 B	-rw-r--r--	2025-09-04 09:37
bits.h	447 B	-rw-r--r--	2025-09-04 09:37
blkpg.h	904 B	-rw-r--r--	2025-09-04 09:37
blktrace_api.h	4.59 KB	-rw-r--r--	2025-09-04 09:37
blkzoned.h	6.34 KB	-rw-r--r--	2025-09-04 09:37
bpf.h	272.11 KB	-rw-r--r--	2025-09-04 09:37
bpf_common.h	1.33 KB	-rw-r--r--	2025-09-04 09:37
bpf_perf_event.h	529 B	-rw-r--r--	2025-09-04 09:37
bpfilter.h	465 B	-rw-r--r--	2025-09-04 09:37
bpqether.h	981 B	-rw-r--r--	2025-09-04 09:37
bsg.h	2.44 KB	-rw-r--r--	2025-09-04 09:37
bt-bmc.h	572 B	-rw-r--r--	2025-09-04 09:37
btf.h	5.46 KB	-rw-r--r--	2025-09-04 09:37
btrfs.h	29.85 KB	-rw-r--r--	2025-09-04 09:37
btrfs_tree.h	25.22 KB	-rw-r--r--	2025-09-04 09:37
cachefiles.h	1.61 KB	-rw-r--r--	2025-09-04 09:37
can.h	11.03 KB	-rw-r--r--	2025-09-04 09:37
capability.h	13.17 KB	-rw-r--r--	2025-09-04 09:37
capi.h	3.05 KB	-rw-r--r--	2025-09-04 09:37
cciss_defs.h	3.2 KB	-rw-r--r--	2025-09-04 09:37
cciss_ioctl.h	2.7 KB	-rw-r--r--	2025-09-04 09:37
ccs.h	767 B	-rw-r--r--	2025-09-04 09:37
cdrom.h	28.87 KB	-rw-r--r--	2025-09-04 09:37
cec-funcs.h	53.14 KB	-rw-r--r--	2025-09-04 09:37
cec.h	40.47 KB	-rw-r--r--	2025-09-04 09:37
cfm_bridge.h	1.42 KB	-rw-r--r--	2025-09-04 09:37
cgroupstats.h	2.17 KB	-rw-r--r--	2025-09-04 09:37
chio.h	5.16 KB	-rw-r--r--	2025-09-04 09:37
close_range.h	377 B	-rw-r--r--	2025-09-04 09:37
cm4000_cs.h	1.76 KB	-rw-r--r--	2025-09-04 09:37
cn_proc.h	4.05 KB	-rw-r--r--	2025-09-04 09:37
coda.h	17.79 KB	-rw-r--r--	2025-09-04 09:37
coff.h	12.25 KB	-rw-r--r--	2025-09-04 09:37
connector.h	2.2 KB	-rw-r--r--	2025-09-04 09:37
const.h	987 B	-rw-r--r--	2025-09-04 09:37
coresight-stm.h	747 B	-rw-r--r--	2025-09-04 09:37
cramfs_fs.h	3.47 KB	-rw-r--r--	2025-09-04 09:37
cryptouser.h	5.2 KB	-rw-r--r--	2025-09-04 09:37
cuda.h	905 B	-rw-r--r--	2025-09-04 09:37
cxl_mem.h	7.73 KB	-rw-r--r--	2025-09-04 09:37
cycx_cfm.h	2.92 KB	-rw-r--r--	2025-09-04 09:37
dcbnl.h	24.7 KB	-rw-r--r--	2025-09-04 09:37
dccp.h	6.29 KB	-rw-r--r--	2025-09-04 09:37
devlink.h	22.3 KB	-rw-r--r--	2025-09-04 09:37
dlm.h	2.49 KB	-rw-r--r--	2025-09-04 09:37
dlm_device.h	2.48 KB	-rw-r--r--	2025-09-04 09:37
dlm_netlink.h	1.13 KB	-rw-r--r--	2025-09-04 09:37
dlm_plock.h	894 B	-rw-r--r--	2025-09-04 09:37
dlmconstants.h	4.96 KB	-rw-r--r--	2025-09-04 09:37
dm-ioctl.h	11.48 KB	-rw-r--r--	2025-09-04 09:37
dm-log-userspace.h	14.83 KB	-rw-r--r--	2025-09-04 09:37
dma-buf.h	5.12 KB	-rw-r--r--	2025-09-04 09:37
dma-heap.h	1.36 KB	-rw-r--r--	2025-09-04 09:37
dn.h	4.53 KB	-rw-r--r--	2025-09-04 09:37
dns_resolver.h	3.86 KB	-rw-r--r--	2025-09-04 09:37
dpll.h	7.19 KB	-rw-r--r--	2025-09-04 09:37
dqblk_xfs.h	9.17 KB	-rw-r--r--	2025-09-04 09:37
edd.h	5.47 KB	-rw-r--r--	2025-09-04 09:37
efs_fs_sb.h	2.17 KB	-rw-r--r--	2025-09-04 09:37
elf-em.h	2.57 KB	-rw-r--r--	2025-09-04 09:37
elf-fdpic.h	1.1 KB	-rw-r--r--	2025-09-04 09:37
elf.h	14.69 KB	-rw-r--r--	2025-09-04 09:37
errno.h	23 B	-rw-r--r--	2025-09-04 09:37
errqueue.h	1.94 KB	-rw-r--r--	2025-09-04 09:37
erspan.h	1.03 KB	-rw-r--r--	2025-09-04 09:37
ethtool.h	100.09 KB	-rw-r--r--	2025-09-04 09:37
ethtool_netlink.h	29.87 KB	-rw-r--r--	2025-09-04 09:37
eventfd.h	264 B	-rw-r--r--	2025-09-04 09:37
eventpoll.h	2.84 KB	-rw-r--r--	2025-09-04 09:37
f2fs.h	3.22 KB	-rw-r--r--	2025-09-04 09:37
fadvise.h	842 B	-rw-r--r--	2025-09-04 09:37
falloc.h	3.5 KB	-rw-r--r--	2025-09-04 09:37
fanotify.h	6.64 KB	-rw-r--r--	2025-09-04 09:37
fb.h	16.09 KB	-rw-r--r--	2025-09-04 09:37
fcntl.h	4.22 KB	-rw-r--r--	2025-09-04 09:37
fd.h	11.83 KB	-rw-r--r--	2025-09-04 09:37
fdreg.h	5.24 KB	-rw-r--r--	2025-09-04 09:37
fib_rules.h	1.99 KB	-rw-r--r--	2025-09-04 09:37
fiemap.h	2.71 KB	-rw-r--r--	2025-09-04 09:37
filter.h	2.16 KB	-rw-r--r--	2025-09-04 09:37
firewire-cdev.h	43.2 KB	-rw-r--r--	2025-09-04 09:37
firewire-constants.h	3.16 KB	-rw-r--r--	2025-09-04 09:37
fou.h	819 B	-rw-r--r--	2025-09-04 09:37
fpga-dfl.h	8.52 KB	-rw-r--r--	2025-09-04 09:37
fs.h	12.88 KB	-rw-r--r--	2025-09-04 09:37
fscrypt.h	6.41 KB	-rw-r--r--	2025-09-04 09:37
fsi.h	2.2 KB	-rw-r--r--	2025-09-04 09:37
fsl_hypervisor.h	7.13 KB	-rw-r--r--	2025-09-04 09:37
fsl_mc.h	734 B	-rw-r--r--	2025-09-04 09:37
fsmap.h	4.29 KB	-rw-r--r--	2025-09-04 09:37
fsverity.h	3.11 KB	-rw-r--r--	2025-09-04 09:37
fuse.h	25.36 KB	-rw-r--r--	2025-09-04 09:37
futex.h	5.98 KB	-rw-r--r--	2025-09-04 09:37
gameport.h	897 B	-rw-r--r--	2025-09-04 09:37
gen_stats.h	1.49 KB	-rw-r--r--	2025-09-04 09:37
genetlink.h	2.19 KB	-rw-r--r--	2025-09-04 09:37
gfs2_ondisk.h	14.43 KB	-rw-r--r--	2025-09-04 09:37
gpio.h	19.46 KB	-rw-r--r--	2025-09-04 09:37
gsmmux.h	4.4 KB	-rw-r--r--	2025-09-04 09:37
gtp.h	734 B	-rw-r--r--	2025-09-04 09:37
handshake.h	1.61 KB	-rw-r--r--	2025-09-04 09:37
hash_info.h	971 B	-rw-r--r--	2025-09-04 09:37
hdlc.h	637 B	-rw-r--r--	2025-09-04 09:37
hdlcdrv.h	2.84 KB	-rw-r--r--	2025-09-04 09:37
hdreg.h	22.17 KB	-rw-r--r--	2025-09-04 09:37
hid.h	2.04 KB	-rw-r--r--	2025-09-04 09:37
hiddev.h	6.2 KB	-rw-r--r--	2025-09-04 09:37
hidraw.h	1.95 KB	-rw-r--r--	2025-09-04 09:37
hpet.h	743 B	-rw-r--r--	2025-09-04 09:37
hsr_netlink.h	1.08 KB	-rw-r--r--	2025-09-04 09:37
hw_breakpoint.h	742 B	-rw-r--r--	2025-09-04 09:37
hyperv.h	10.89 KB	-rw-r--r--	2025-09-04 09:37
i2c-dev.h	1.83 KB	-rw-r--r--	2025-09-04 09:37
i2c.h	6.73 KB	-rw-r--r--	2025-09-04 09:37
i2o-dev.h	11.28 KB	-rw-r--r--	2025-09-04 09:37
i8k.h	1.49 KB	-rw-r--r--	2025-09-04 09:37
icmp.h	4.67 KB	-rw-r--r--	2025-09-04 09:37
icmpv6.h	4.2 KB	-rw-r--r--	2025-09-04 09:37
idxd.h	9.11 KB	-rw-r--r--	2025-09-04 09:37
if.h	10.67 KB	-rw-r--r--	2025-09-04 09:37
if_addr.h	1.84 KB	-rw-r--r--	2025-09-04 09:37
if_addrlabel.h	721 B	-rw-r--r--	2025-09-04 09:37
if_alg.h	1.53 KB	-rw-r--r--	2025-09-04 09:37
if_arcnet.h	3.63 KB	-rw-r--r--	2025-09-04 09:37
if_arp.h	6.41 KB	-rw-r--r--	2025-09-04 09:37
if_bonding.h	5.02 KB	-rw-r--r--	2025-09-04 09:37
if_bridge.h	20.18 KB	-rw-r--r--	2025-09-04 09:37
if_cablemodem.h	986 B	-rw-r--r--	2025-09-04 09:37
if_eql.h	1.32 KB	-rw-r--r--	2025-09-04 09:37
if_ether.h	8.21 KB	-rw-r--r--	2025-09-04 09:37
if_fc.h	1.7 KB	-rw-r--r--	2025-09-04 09:37
if_fddi.h	4.27 KB	-rw-r--r--	2025-09-04 09:37
if_hippi.h	4.14 KB	-rw-r--r--	2025-09-04 09:37
if_infiniband.h	1.22 KB	-rw-r--r--	2025-09-04 09:37
if_link.h	52.83 KB	-rw-r--r--	2025-09-04 09:37
if_ltalk.h	210 B	-rw-r--r--	2025-09-04 09:37
if_macsec.h	6.35 KB	-rw-r--r--	2025-09-04 09:37
if_packet.h	7.99 KB	-rw-r--r--	2025-09-04 09:37
if_phonet.h	424 B	-rw-r--r--	2025-09-04 09:37
if_plip.h	660 B	-rw-r--r--	2025-09-04 09:37
if_ppp.h	29 B	-rw-r--r--	2025-09-04 09:37
if_pppol2tp.h	3.23 KB	-rw-r--r--	2025-09-04 09:37
if_pppox.h	4.76 KB	-rw-r--r--	2025-09-04 09:37
if_slip.h	872 B	-rw-r--r--	2025-09-04 09:37
if_team.h	2.54 KB	-rw-r--r--	2025-09-04 09:37
if_tun.h	4 KB	-rw-r--r--	2025-09-04 09:37
if_tunnel.h	5.36 KB	-rw-r--r--	2025-09-04 09:37
if_vlan.h	1.79 KB	-rw-r--r--	2025-09-04 09:37
if_x25.h	881 B	-rw-r--r--	2025-09-04 09:37
if_xdp.h	4.89 KB	-rw-r--r--	2025-09-04 09:37
ife.h	351 B	-rw-r--r--	2025-09-04 09:37
igmp.h	2.99 KB	-rw-r--r--	2025-09-04 09:37
ila.h	1.22 KB	-rw-r--r--	2025-09-04 09:37
in.h	10.15 KB	-rw-r--r--	2025-09-04 09:37
in6.h	7.36 KB	-rw-r--r--	2025-09-04 09:37
in_route.h	936 B	-rw-r--r--	2025-09-04 09:37
inet_diag.h	4.9 KB	-rw-r--r--	2025-09-04 09:37
inotify.h	3.21 KB	-rw-r--r--	2025-09-04 09:37
input-event-codes.h	29.5 KB	-rw-r--r--	2025-09-04 09:37
input.h	15.84 KB	-rw-r--r--	2025-09-04 09:37
io_uring.h	20.4 KB	-rw-r--r--	2025-09-04 09:37
ioctl.h	163 B	-rw-r--r--	2025-09-04 09:37
iommufd.h	28.39 KB	-rw-r--r--	2025-09-04 09:37
ioprio.h	4.08 KB	-rw-r--r--	2025-09-04 09:37
ip.h	4.7 KB	-rw-r--r--	2025-09-04 09:37
ip6_tunnel.h	1.91 KB	-rw-r--r--	2025-09-04 09:37
ip_vs.h	13.8 KB	-rw-r--r--	2025-09-04 09:37
ipc.h	2.05 KB	-rw-r--r--	2025-09-04 09:37
ipmi.h	15.08 KB	-rw-r--r--	2025-09-04 09:37
ipmi_bmc.h	488 B	-rw-r--r--	2025-09-04 09:37
ipmi_msgdefs.h	3.35 KB	-rw-r--r--	2025-09-04 09:37
ipmi_ssif_bmc.h	441 B	-rw-r--r--	2025-09-04 09:37
ipsec.h	947 B	-rw-r--r--	2025-09-04 09:37
ipv6.h	4.07 KB	-rw-r--r--	2025-09-04 09:37
ipv6_route.h	1.86 KB	-rw-r--r--	2025-09-04 09:37
ipx.h	2.29 KB	-rw-r--r--	2025-09-04 09:37
irqnr.h	104 B	-rw-r--r--	2025-09-04 09:37
iso_fs.h	6.33 KB	-rw-r--r--	2025-09-04 09:37
isst_if.h	14.92 KB	-rw-r--r--	2025-09-04 09:37
ivtv.h	2.95 KB	-rw-r--r--	2025-09-04 09:37
ivtvfb.h	1.18 KB	-rw-r--r--	2025-09-04 09:37
jffs2.h	6.66 KB	-rw-r--r--	2025-09-04 09:37
joystick.h	3.35 KB	-rw-r--r--	2025-09-04 09:37
kcm.h	822 B	-rw-r--r--	2025-09-04 09:37
kcmp.h	522 B	-rw-r--r--	2025-09-04 09:37
kcov.h	1.92 KB	-rw-r--r--	2025-09-04 09:37
kd.h	6.3 KB	-rw-r--r--	2025-09-04 09:37
kdev_t.h	383 B	-rw-r--r--	2025-09-04 09:37
kernel-page-flags.h	900 B	-rw-r--r--	2025-09-04 09:37
kernel.h	194 B	-rw-r--r--	2025-09-04 09:37
kernelcapi.h	1019 B	-rw-r--r--	2025-09-04 09:37
kexec.h	2.05 KB	-rw-r--r--	2025-09-04 09:37
keyboard.h	13.14 KB	-rw-r--r--	2025-09-04 09:37
keyctl.h	5.86 KB	-rw-r--r--	2025-09-04 09:37
kfd_ioctl.h	56.75 KB	-rw-r--r--	2025-09-04 09:37
kfd_sysfs.h	5.1 KB	-rw-r--r--	2025-09-04 09:37
kvm.h	46.76 KB	-rw-r--r--	2025-09-04 09:37
kvm_para.h	1001 B	-rw-r--r--	2025-09-04 09:37
l2tp.h	5.61 KB	-rw-r--r--	2025-09-04 09:37
landlock.h	10.14 KB	-rw-r--r--	2025-09-04 09:37
libc-compat.h	8.09 KB	-rw-r--r--	2025-09-04 09:37
limits.h	937 B	-rw-r--r--	2025-09-04 09:37
lirc.h	7.95 KB	-rw-r--r--	2025-09-04 09:37
llc.h	3.09 KB	-rw-r--r--	2025-09-04 09:37
loadpin.h	834 B	-rw-r--r--	2025-09-04 09:37
loop.h	3.32 KB	-rw-r--r--	2025-09-04 09:37
lp.h	4.09 KB	-rw-r--r--	2025-09-04 09:37
lsm.h	1.51 KB	-rw-r--r--	2025-09-04 09:37
lwtunnel.h	2.31 KB	-rw-r--r--	2025-09-04 09:37
magic.h	3.73 KB	-rw-r--r--	2025-09-04 09:37
major.h	4.55 KB	-rw-r--r--	2025-09-04 09:37
map_to_7segment.h	6.45 KB	-rw-r--r--	2025-09-04 09:37
matroxfb.h	1.43 KB	-rw-r--r--	2025-09-04 09:37
max2175.h	1.01 KB	-rw-r--r--	2025-09-04 09:37
mdio.h	23.78 KB	-rw-r--r--	2025-09-04 09:37
media-bus-format.h	6.75 KB	-rw-r--r--	2025-09-04 09:37
media.h	12.46 KB	-rw-r--r--	2025-09-04 09:37
mei.h	3.4 KB	-rw-r--r--	2025-09-04 09:37
mei_uuid.h	738 B	-rw-r--r--	2025-09-04 09:37
membarrier.h	9.14 KB	-rw-r--r--	2025-09-04 09:37
memfd.h	1.43 KB	-rw-r--r--	2025-09-04 09:37
mempolicy.h	2.51 KB	-rw-r--r--	2025-09-04 09:37
meye.h	2.47 KB	-rw-r--r--	2025-09-04 09:37
mii.h	9.27 KB	-rw-r--r--	2025-09-04 09:37
minix_fs.h	2.07 KB	-rw-r--r--	2025-09-04 09:37
mman.h	1.75 KB	-rw-r--r--	2025-09-04 09:37
mmtimer.h	2.07 KB	-rw-r--r--	2025-09-04 09:37
module.h	293 B	-rw-r--r--	2025-09-04 09:37
mount.h	4.9 KB	-rw-r--r--	2025-09-04 09:37
mpls.h	2.25 KB	-rw-r--r--	2025-09-04 09:37
mpls_iptunnel.h	761 B	-rw-r--r--	2025-09-04 09:37
mptcp.h	3.67 KB	-rw-r--r--	2025-09-04 09:37
mptcp_pm.h	4.3 KB	-rw-r--r--	2025-09-04 09:37
mqueue.h	2.15 KB	-rw-r--r--	2025-09-04 09:37
mroute.h	5.78 KB	-rw-r--r--	2025-09-04 09:37
mroute6.h	4.81 KB	-rw-r--r--	2025-09-04 09:37
mrp_bridge.h	1.67 KB	-rw-r--r--	2025-09-04 09:37
msdos_fs.h	6.57 KB	-rw-r--r--	2025-09-04 09:37
msg.h	3.31 KB	-rw-r--r--	2025-09-04 09:37
mtio.h	7.98 KB	-rw-r--r--	2025-09-04 09:37
nbd-netlink.h	2.35 KB	-rw-r--r--	2025-09-04 09:37
nbd.h	3.77 KB	-rw-r--r--	2025-09-04 09:37
ncsi.h	4.71 KB	-rw-r--r--	2025-09-04 09:37
ndctl.h	6.67 KB	-rw-r--r--	2025-09-04 09:37
neighbour.h	5.91 KB	-rw-r--r--	2025-09-04 09:37
net.h	2.04 KB	-rw-r--r--	2025-09-04 09:37
net_dropmon.h	2.85 KB	-rw-r--r--	2025-09-04 09:37
net_namespace.h	715 B	-rw-r--r--	2025-09-04 09:37
net_tstamp.h	5.97 KB	-rw-r--r--	2025-09-04 09:37
netconf.h	614 B	-rw-r--r--	2025-09-04 09:37
netdev.h	5.39 KB	-rw-r--r--	2025-09-04 09:37
netdevice.h	2.2 KB	-rw-r--r--	2025-09-04 09:37
netfilter.h	1.69 KB	-rw-r--r--	2025-09-04 09:37
netfilter_arp.h	445 B	-rw-r--r--	2025-09-04 09:37
netfilter_bridge.h	1.14 KB	-rw-r--r--	2025-09-04 09:37
netfilter_decnet.h	1.72 KB	-rw-r--r--	2025-09-04 09:37
netfilter_ipv4.h	1.45 KB	-rw-r--r--	2025-09-04 09:37
netfilter_ipv6.h	1.35 KB	-rw-r--r--	2025-09-04 09:37
netlink.h	12.09 KB	-rw-r--r--	2025-09-04 09:37
netlink_diag.h	1.49 KB	-rw-r--r--	2025-09-04 09:37
netrom.h	807 B	-rw-r--r--	2025-09-04 09:37
nexthop.h	3.97 KB	-rw-r--r--	2025-09-04 09:37
nfc.h	10.95 KB	-rw-r--r--	2025-09-04 09:37
nfs.h	4.36 KB	-rw-r--r--	2025-09-04 09:37
nfs2.h	1.43 KB	-rw-r--r--	2025-09-04 09:37
nfs3.h	2.4 KB	-rw-r--r--	2025-09-04 09:37
nfs4.h	6.54 KB	-rw-r--r--	2025-09-04 09:37
nfs4_mount.h	1.89 KB	-rw-r--r--	2025-09-04 09:37
nfs_fs.h	1.62 KB	-rw-r--r--	2025-09-04 09:37
nfs_idmap.h	2.19 KB	-rw-r--r--	2025-09-04 09:37
nfs_mount.h	2.09 KB	-rw-r--r--	2025-09-04 09:37
nfsacl.h	718 B	-rw-r--r--	2025-09-04 09:37
nfsd_netlink.h	1.95 KB	-rw-r--r--	2025-09-04 09:37
nilfs2_api.h	7.41 KB	-rw-r--r--	2025-09-04 09:37
nilfs2_ondisk.h	17.66 KB	-rw-r--r--	2025-09-04 09:37
nitro_enclaves.h	12.85 KB	-rw-r--r--	2025-09-04 09:37
nl80211.h	338.95 KB	-rw-r--r--	2025-09-04 09:37
nsfs.h	639 B	-rw-r--r--	2025-09-04 09:37
nubus.h	8 KB	-rw-r--r--	2025-09-04 09:37
nvme_ioctl.h	2.43 KB	-rw-r--r--	2025-09-04 09:37
nvram.h	532 B	-rw-r--r--	2025-09-04 09:37
omap3isp.h	20.36 KB	-rw-r--r--	2025-09-04 09:37
omapfb.h	5.78 KB	-rw-r--r--	2025-09-04 09:37
oom.h	511 B	-rw-r--r--	2025-09-04 09:37
openat2.h	1.42 KB	-rw-r--r--	2025-09-04 09:37
openvswitch.h	40.41 KB	-rw-r--r--	2025-09-04 09:37
packet_diag.h	1.63 KB	-rw-r--r--	2025-09-04 09:37
param.h	141 B	-rw-r--r--	2025-09-04 09:37
parport.h	3.56 KB	-rw-r--r--	2025-09-04 09:37
patchkey.h	892 B	-rw-r--r--	2025-09-04 09:37
pci.h	1.35 KB	-rw-r--r--	2025-09-04 09:37
pci_regs.h	60.58 KB	-rw-r--r--	2025-09-04 09:37
pcitest.h	920 B	-rw-r--r--	2025-09-04 09:37
perf_event.h	42.43 KB	-rw-r--r--	2025-09-04 09:37
personality.h	2.05 KB	-rw-r--r--	2025-09-04 09:37
pfkeyv2.h	10.32 KB	-rw-r--r--	2025-09-04 09:37
pfrut.h	7.8 KB	-rw-r--r--	2025-09-04 09:37
pg.h	2.34 KB	-rw-r--r--	2025-09-04 09:37
phantom.h	1.62 KB	-rw-r--r--	2025-09-04 09:37
phonet.h	4.57 KB	-rw-r--r--	2025-09-04 09:37
pidfd.h	256 B	-rw-r--r--	2025-09-04 09:37
pkt_cls.h	18.65 KB	-rw-r--r--	2025-09-04 09:37
pkt_sched.h	28.66 KB	-rw-r--r--	2025-09-04 09:37
pktcdvd.h	2.63 KB	-rw-r--r--	2025-09-04 09:37
pmu.h	5.32 KB	-rw-r--r--	2025-09-04 09:37
poll.h	22 B	-rw-r--r--	2025-09-04 09:37
posix_acl.h	1.22 KB	-rw-r--r--	2025-09-04 09:37
posix_acl_xattr.h	1.09 KB	-rw-r--r--	2025-09-04 09:37
posix_types.h	1.07 KB	-rw-r--r--	2025-09-04 09:37
ppdev.h	3.21 KB	-rw-r--r--	2025-09-04 09:37
ppp-comp.h	2.47 KB	-rw-r--r--	2025-09-04 09:37
ppp-ioctl.h	5.59 KB	-rw-r--r--	2025-09-04 09:37
ppp_defs.h	5.43 KB	-rw-r--r--	2025-09-04 09:37
pps.h	4.62 KB	-rw-r--r--	2025-09-04 09:37
pr.h	1.59 KB	-rw-r--r--	2025-09-04 09:37
prctl.h	10.81 KB	-rw-r--r--	2025-09-04 09:37
psample.h	2.57 KB	-rw-r--r--	2025-09-04 09:37
psci.h	5.02 KB	-rw-r--r--	2025-09-04 09:37
psp-dbc.h	5.16 KB	-rw-r--r--	2025-09-04 09:37
psp-sev.h	6.26 KB	-rw-r--r--	2025-09-04 09:37
ptp_clock.h	7.35 KB	-rw-r--r--	2025-09-04 09:37
ptrace.h	4.29 KB	-rw-r--r--	2025-09-04 09:37
qemu_fw_cfg.h	2.41 KB	-rw-r--r--	2025-09-04 09:37
qnx4_fs.h	2.27 KB	-rw-r--r--	2025-09-04 09:37
qnxtypes.h	624 B	-rw-r--r--	2025-09-04 09:37
qrtr.h	893 B	-rw-r--r--	2025-09-04 09:37
quota.h	6.16 KB	-rw-r--r--	2025-09-04 09:37
radeonfb.h	360 B	-rw-r--r--	2025-09-04 09:37
random.h	1.38 KB	-rw-r--r--	2025-09-04 09:37
rds.h	10.91 KB	-rw-r--r--	2025-09-04 09:37
reboot.h	1.31 KB	-rw-r--r--	2025-09-04 09:37
reiserfs_fs.h	775 B	-rw-r--r--	2025-09-04 09:37
reiserfs_xattr.h	533 B	-rw-r--r--	2025-09-04 09:37
remoteproc_cdev.h	1.08 KB	-rw-r--r--	2025-09-04 09:37
resource.h	2.32 KB	-rw-r--r--	2025-09-04 09:37
rfkill.h	6.45 KB	-rw-r--r--	2025-09-04 09:37
rio_cm_cdev.h	3.17 KB	-rw-r--r--	2025-09-04 09:37
rio_mport_cdev.h	9.11 KB	-rw-r--r--	2025-09-04 09:37
rkisp1-config.h	30.63 KB	-rw-r--r--	2025-09-04 09:37
romfs_fs.h	1.21 KB	-rw-r--r--	2025-09-04 09:37
rose.h	2.18 KB	-rw-r--r--	2025-09-04 09:37
route.h	2.28 KB	-rw-r--r--	2025-09-04 09:37
rpl.h	814 B	-rw-r--r--	2025-09-04 09:37
rpl_iptunnel.h	424 B	-rw-r--r--	2025-09-04 09:37
rpmsg.h	1.03 KB	-rw-r--r--	2025-09-04 09:37
rpmsg_types.h	288 B	-rw-r--r--	2025-09-04 09:37
rseq.h	4.79 KB	-rw-r--r--	2025-09-04 09:37
rtc.h	5.19 KB	-rw-r--r--	2025-09-04 09:37
rtnetlink.h	20.8 KB	-rw-r--r--	2025-09-04 09:37
rxrpc.h	4.81 KB	-rw-r--r--	2025-09-04 09:37
scc.h	4.52 KB	-rw-r--r--	2025-09-04 09:37
sched.h	6.12 KB	-rw-r--r--	2025-09-04 09:37
scif_ioctl.h	6.23 KB	-rw-r--r--	2025-09-04 09:37
screen_info.h	2.42 KB	-rw-r--r--	2025-09-04 09:37
sctp.h	35.18 KB	-rw-r--r--	2025-09-04 09:37
seccomp.h	5.6 KB	-rw-r--r--	2025-09-04 09:37
securebits.h	2.64 KB	-rw-r--r--	2025-09-04 09:37
sed-opal.h	5.29 KB	-rw-r--r--	2025-09-04 09:37
seg6.h	1.14 KB	-rw-r--r--	2025-09-04 09:37
seg6_genl.h	589 B	-rw-r--r--	2025-09-04 09:37
seg6_hmac.h	423 B	-rw-r--r--	2025-09-04 09:37
seg6_iptunnel.h	984 B	-rw-r--r--	2025-09-04 09:37
seg6_local.h	3.78 KB	-rw-r--r--	2025-09-04 09:37
selinux_netlink.h	1.17 KB	-rw-r--r--	2025-09-04 09:37
sem.h	2.98 KB	-rw-r--r--	2025-09-04 09:37
serial.h	4.9 KB	-rw-r--r--	2025-09-04 09:37
serial_core.h	4.93 KB	-rw-r--r--	2025-09-04 09:37
serial_reg.h	15.65 KB	-rw-r--r--	2025-09-04 09:37
serio.h	2.09 KB	-rw-r--r--	2025-09-04 09:37
sev-guest.h	2.47 KB	-rw-r--r--	2025-09-04 09:37
shm.h	3.71 KB	-rw-r--r--	2025-09-04 09:37
signal.h	388 B	-rw-r--r--	2025-09-04 09:37
signalfd.h	1.2 KB	-rw-r--r--	2025-09-04 09:37
smc.h	8.31 KB	-rw-r--r--	2025-09-04 09:37
smc_diag.h	2.77 KB	-rw-r--r--	2025-09-04 09:37
smiapp.h	1.03 KB	-rw-r--r--	2025-09-04 09:37
snmp.h	13.92 KB	-rw-r--r--	2025-09-04 09:37
sock_diag.h	1.27 KB	-rw-r--r--	2025-09-04 09:37
socket.h	919 B	-rw-r--r--	2025-09-04 09:37
sockios.h	6.69 KB	-rw-r--r--	2025-09-04 09:37
sonet.h	2.24 KB	-rw-r--r--	2025-09-04 09:37
sonypi.h	5.18 KB	-rw-r--r--	2025-09-04 09:37
sound.h	1.21 KB	-rw-r--r--	2025-09-04 09:37
soundcard.h	44.96 KB	-rw-r--r--	2025-09-04 09:37
stat.h	7.23 KB	-rw-r--r--	2025-09-04 09:37
stddef.h	1.69 KB	-rw-r--r--	2025-09-04 09:37
stm.h	1.25 KB	-rw-r--r--	2025-09-04 09:37
string.h	238 B	-rw-r--r--	2025-09-04 09:37
suspend_ioctls.h	1.4 KB	-rw-r--r--	2025-09-04 09:37
swab.h	6.76 KB	-rw-r--r--	2025-09-04 09:37
switchtec_ioctl.h	5.14 KB	-rw-r--r--	2025-09-04 09:37
sync_file.h	3.49 KB	-rw-r--r--	2025-09-04 09:37
synclink.h	8.77 KB	-rw-r--r--	2025-09-04 09:37
sysctl.h	25.3 KB	-rw-r--r--	2025-09-04 09:37
sysinfo.h	1.02 KB	-rw-r--r--	2025-09-04 09:37
target_core_user.h	4.52 KB	-rw-r--r--	2025-09-04 09:37
taskstats.h	8.13 KB	-rw-r--r--	2025-09-04 09:37
tcp.h	11.65 KB	-rw-r--r--	2025-09-04 09:37
tcp_metrics.h	1.94 KB	-rw-r--r--	2025-09-04 09:37
tdx-guest.h	1.27 KB	-rw-r--r--	2025-09-04 09:37
tee.h	13.09 KB	-rw-r--r--	2025-09-04 09:37
termios.h	172 B	-rw-r--r--	2025-09-04 09:37
thermal.h	3.23 KB	-rw-r--r--	2025-09-04 09:37
time.h	1.71 KB	-rw-r--r--	2025-09-04 09:37
time_types.h	1.24 KB	-rw-r--r--	2025-09-04 09:37
timerfd.h	936 B	-rw-r--r--	2025-09-04 09:37
times.h	278 B	-rw-r--r--	2025-09-04 09:37
timex.h	7.63 KB	-rw-r--r--	2025-09-04 09:37
tiocl.h	1.69 KB	-rw-r--r--	2025-09-04 09:37
tipc.h	8.62 KB	-rw-r--r--	2025-09-04 09:37
tipc_config.h	14.52 KB	-rw-r--r--	2025-09-04 09:37
tipc_netlink.h	9.17 KB	-rw-r--r--	2025-09-04 09:37
tipc_sockets_diag.h	468 B	-rw-r--r--	2025-09-04 09:37
tls.h	7.06 KB	-rw-r--r--	2025-09-04 09:37
toshiba.h	1.88 KB	-rw-r--r--	2025-09-04 09:37
tps6594_pfsm.h	1.13 KB	-rw-r--r--	2025-09-04 09:37
tty.h	1.55 KB	-rw-r--r--	2025-09-04 09:37
tty_flags.h	4.4 KB	-rw-r--r--	2025-09-04 09:37
types.h	1.6 KB	-rw-r--r--	2025-09-04 09:37
udf_fs_i.h	697 B	-rw-r--r--	2025-09-04 09:37
udmabuf.h	643 B	-rw-r--r--	2025-09-04 09:37
udp.h	1.65 KB	-rw-r--r--	2025-09-04 09:37
uhid.h	4.54 KB	-rw-r--r--	2025-09-04 09:37
uinput.h	9.04 KB	-rw-r--r--	2025-09-04 09:37
uio.h	732 B	-rw-r--r--	2025-09-04 09:37
uleds.h	798 B	-rw-r--r--	2025-09-04 09:37
ultrasound.h	4.46 KB	-rw-r--r--	2025-09-04 09:37
um_timetravel.h	3.87 KB	-rw-r--r--	2025-09-04 09:37
un.h	384 B	-rw-r--r--	2025-09-04 09:37
unistd.h	220 B	-rw-r--r--	2025-09-04 09:37
unix_diag.h	1.3 KB	-rw-r--r--	2025-09-04 09:37
usbdevice_fs.h	8.12 KB	-rw-r--r--	2025-09-04 09:37
usbip.h	1.47 KB	-rw-r--r--	2025-09-04 09:37
userfaultfd.h	10.68 KB	-rw-r--r--	2025-09-04 09:37
userio.h	1.48 KB	-rw-r--r--	2025-09-04 09:37
utime.h	223 B	-rw-r--r--	2025-09-04 09:37
utsname.h	669 B	-rw-r--r--	2025-09-04 09:37
uuid.h	28 B	-rw-r--r--	2025-09-04 09:37
uvcvideo.h	2.57 KB	-rw-r--r--	2025-09-04 09:37
v4l2-common.h	2.01 KB	-rw-r--r--	2025-09-04 09:37
v4l2-controls.h	94.59 KB	-rw-r--r--	2025-09-04 09:37
v4l2-dv-timings.h	30.39 KB	-rw-r--r--	2025-09-04 09:37
v4l2-mediabus.h	5.3 KB	-rw-r--r--	2025-09-04 09:37
v4l2-subdev.h	9.76 KB	-rw-r--r--	2025-09-04 09:37
vbox_err.h	7.09 KB	-rw-r--r--	2025-09-04 09:37
vbox_vmmdev_types.h	11.38 KB	-rw-r--r--	2025-09-04 09:37
vboxguest.h	9.15 KB	-rw-r--r--	2025-09-04 09:37
vdpa.h	1.74 KB	-rw-r--r--	2025-09-04 09:37
vduse.h	9.58 KB	-rw-r--r--	2025-09-04 09:37
version.h	374 B	-rw-r--r--	2025-09-04 09:37
veth.h	224 B	-rw-r--r--	2025-09-04 09:37
vfio.h	70.12 KB	-rw-r--r--	2025-09-04 09:37
vfio_ccw.h	1.29 KB	-rw-r--r--	2025-09-04 09:37
vfio_zdev.h	2.48 KB	-rw-r--r--	2025-09-04 09:37
vhost.h	8.24 KB	-rw-r--r--	2025-09-04 09:37
vhost_types.h	4.77 KB	-rw-r--r--	2025-09-04 09:37
videodev2.h	98.83 KB	-rw-r--r--	2025-09-04 09:37
virtio_9p.h	2 KB	-rw-r--r--	2025-09-04 09:37
virtio_balloon.h	5.16 KB	-rw-r--r--	2025-09-04 09:37
virtio_blk.h	9.75 KB	-rw-r--r--	2025-09-04 09:37
virtio_bt.h	910 B	-rw-r--r--	2025-09-04 09:37
virtio_config.h	4.36 KB	-rw-r--r--	2025-09-04 09:37
virtio_console.h	3.08 KB	-rw-r--r--	2025-09-04 09:37
virtio_crypto.h	13.56 KB	-rw-r--r--	2025-09-04 09:37
virtio_fs.h	573 B	-rw-r--r--	2025-09-04 09:37
virtio_gpio.h	1.7 KB	-rw-r--r--	2025-09-04 09:37
virtio_gpu.h	11.28 KB	-rw-r--r--	2025-09-04 09:37
virtio_i2c.h	1.16 KB	-rw-r--r--	2025-09-04 09:37
virtio_ids.h	3.7 KB	-rw-r--r--	2025-09-04 09:37
virtio_input.h	2.46 KB	-rw-r--r--	2025-09-04 09:37
virtio_iommu.h	3.84 KB	-rw-r--r--	2025-09-04 09:37
virtio_mem.h	6.99 KB	-rw-r--r--	2025-09-04 09:37
virtio_mmio.h	4.85 KB	-rw-r--r--	2025-09-04 09:37
virtio_net.h	14.72 KB	-rw-r--r--	2025-09-04 09:37
virtio_pci.h	7.3 KB	-rw-r--r--	2025-09-04 09:37
virtio_pcidev.h	2.33 KB	-rw-r--r--	2025-09-04 09:37
virtio_pmem.h	641 B	-rw-r--r--	2025-09-04 09:37
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x25.h	3.48 KB	-rw-r--r--	2025-09-04 09:37
xattr.h	2.95 KB	-rw-r--r--	2025-09-04 09:37
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xilinx-v4l2-controls.h	2.91 KB	-rw-r--r--	2025-09-04 09:37
zorro.h	3.22 KB	-rw-r--r--	2025-09-04 09:37
zorro_ids.h	29.26 KB	-rw-r--r--	2025-09-04 09:37

Rename

/* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */
/*
 * include/linux/serial_reg.h
 *
 * Copyright (C) 1992, 1994 by Theodore Ts'o.
 * 
 * Redistribution of this file is permitted under the terms of the GNU 
 * Public License (GPL)
 * 
 * These are the UART port assignments, expressed as offsets from the base
 * register.  These assignments should hold for any serial port based on
 * a 8250, 16450, or 16550(A).
 */

#ifndef _LINUX_SERIAL_REG_H
#define _LINUX_SERIAL_REG_H

/*
 * DLAB=0
 */
#define UART_RX		0	/* In:  Receive buffer */
#define UART_TX		0	/* Out: Transmit buffer */

#define UART_IER	1	/* Out: Interrupt Enable Register */
#define UART_IER_MSI		0x08 /* Enable Modem status interrupt */
#define UART_IER_RLSI		0x04 /* Enable receiver line status interrupt */
#define UART_IER_THRI		0x02 /* Enable Transmitter holding register int. */
#define UART_IER_RDI		0x01 /* Enable receiver data interrupt */
/*
 * Sleep mode for ST16650 and TI16750.  For the ST16650, EFR[4]=1
 */
#define UART_IERX_SLEEP		0x10 /* Enable sleep mode */

#define UART_IIR	2	/* In:  Interrupt ID Register */
#define UART_IIR_NO_INT		0x01 /* No interrupts pending */
#define UART_IIR_ID		0x0e /* Mask for the interrupt ID */
#define UART_IIR_MSI		0x00 /* Modem status interrupt */
#define UART_IIR_THRI		0x02 /* Transmitter holding register empty */
#define UART_IIR_RDI		0x04 /* Receiver data interrupt */
#define UART_IIR_RLSI		0x06 /* Receiver line status interrupt */

#define UART_IIR_BUSY		0x07 /* DesignWare APB Busy Detect */

#define UART_IIR_RX_TIMEOUT	0x0c /* OMAP RX Timeout interrupt */
#define UART_IIR_XOFF		0x10 /* OMAP XOFF/Special Character */
#define UART_IIR_CTS_RTS_DSR	0x20 /* OMAP CTS/RTS/DSR Change */
#define UART_IIR_64BYTE_FIFO	0x20 /* 16750 64 bytes FIFO */
#define UART_IIR_FIFO_ENABLED	0xc0 /* FIFOs enabled / port type identification */
#define  UART_IIR_FIFO_ENABLED_8250	0x00	/* 8250: no FIFO */
#define  UART_IIR_FIFO_ENABLED_16550	0x80	/* 16550: (broken/unusable) FIFO */
#define  UART_IIR_FIFO_ENABLED_16550A	0xc0	/* 16550A: FIFO enabled */
#define  UART_IIR_FIFO_ENABLED_16750	0xe0	/* 16750: 64 bytes FIFO enabled */

#define UART_FCR	2	/* Out: FIFO Control Register */
#define UART_FCR_ENABLE_FIFO	0x01 /* Enable the FIFO */
#define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
#define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
#define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
/*
 * Note: The FIFO trigger levels are chip specific:
 *	RX:76 = 00  01  10  11	TX:54 = 00  01  10  11
 * PC16550D:	 1   4   8  14		xx  xx  xx  xx
 * TI16C550A:	 1   4   8  14          xx  xx  xx  xx
 * TI16C550C:	 1   4   8  14          xx  xx  xx  xx
 * ST16C550:	 1   4   8  14		xx  xx  xx  xx
 * ST16C650:	 8  16  24  28		16   8  24  30	PORT_16650V2
 * NS16C552:	 1   4   8  14		xx  xx  xx  xx
 * ST16C654:	 8  16  56  60		 8  16  32  56	PORT_16654
 * TI16C750:	 1  16  32  56		xx  xx  xx  xx	PORT_16750
 * TI16C752:	 8  16  56  60		 8  16  32  56
 * OX16C950:	16  32 112 120		16  32  64 112	PORT_16C950
 * Tegra:	 1   4   8  14		16   8   4   1	PORT_TEGRA
 */
#define UART_FCR_R_TRIG_00	0x00
#define UART_FCR_R_TRIG_01	0x40
#define UART_FCR_R_TRIG_10	0x80
#define UART_FCR_R_TRIG_11	0xc0
#define UART_FCR_T_TRIG_00	0x00
#define UART_FCR_T_TRIG_01	0x10
#define UART_FCR_T_TRIG_10	0x20
#define UART_FCR_T_TRIG_11	0x30

#define UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
#define UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
#define UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
#define UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
#define UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */
/* 16650 definitions */
#define UART_FCR6_R_TRIGGER_8	0x00 /* Mask for receive trigger set at 1 */
#define UART_FCR6_R_TRIGGER_16	0x40 /* Mask for receive trigger set at 4 */
#define UART_FCR6_R_TRIGGER_24  0x80 /* Mask for receive trigger set at 8 */
#define UART_FCR6_R_TRIGGER_28	0xC0 /* Mask for receive trigger set at 14 */
#define UART_FCR6_T_TRIGGER_16	0x00 /* Mask for transmit trigger set at 16 */
#define UART_FCR6_T_TRIGGER_8	0x10 /* Mask for transmit trigger set at 8 */
#define UART_FCR6_T_TRIGGER_24  0x20 /* Mask for transmit trigger set at 24 */
#define UART_FCR6_T_TRIGGER_30	0x30 /* Mask for transmit trigger set at 30 */
#define UART_FCR7_64BYTE	0x20 /* Go into 64 byte mode (TI16C750 and
					some Freescale UARTs) */

#define UART_FCR_R_TRIG_SHIFT		6
#define UART_FCR_R_TRIG_BITS(x)		\
	(((x) & UART_FCR_TRIGGER_MASK) >> UART_FCR_R_TRIG_SHIFT)
#define UART_FCR_R_TRIG_MAX_STATE	4

#define UART_LCR	3	/* Out: Line Control Register */
/*
 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 
 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
 */
#define UART_LCR_DLAB		0x80 /* Divisor latch access bit */
#define UART_LCR_SBC		0x40 /* Set break control */
#define UART_LCR_SPAR		0x20 /* Stick parity (?) */
#define UART_LCR_EPAR		0x10 /* Even parity select */
#define UART_LCR_PARITY		0x08 /* Parity Enable */
#define UART_LCR_STOP		0x04 /* Stop bits: 0=1 bit, 1=2 bits */
#define UART_LCR_WLEN5		0x00 /* Wordlength: 5 bits */
#define UART_LCR_WLEN6		0x01 /* Wordlength: 6 bits */
#define UART_LCR_WLEN7		0x02 /* Wordlength: 7 bits */
#define UART_LCR_WLEN8		0x03 /* Wordlength: 8 bits */

/*
 * Access to some registers depends on register access / configuration
 * mode.
 */
#define UART_LCR_CONF_MODE_A	UART_LCR_DLAB	/* Configutation mode A */
#define UART_LCR_CONF_MODE_B	0xBF		/* Configutation mode B */

#define UART_MCR	4	/* Out: Modem Control Register */
#define UART_MCR_CLKSEL		0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */
#define UART_MCR_TCRTLR		0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */
#define UART_MCR_XONANY		0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */
#define UART_MCR_AFE		0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
#define UART_MCR_LOOP		0x10 /* Enable loopback test mode */
#define UART_MCR_OUT2		0x08 /* Out2 complement */
#define UART_MCR_OUT1		0x04 /* Out1 complement */
#define UART_MCR_RTS		0x02 /* RTS complement */
#define UART_MCR_DTR		0x01 /* DTR complement */

#define UART_LSR	5	/* In:  Line Status Register */
#define UART_LSR_FIFOE		0x80 /* Fifo error */
#define UART_LSR_TEMT		0x40 /* Transmitter empty */
#define UART_LSR_THRE		0x20 /* Transmit-hold-register empty */
#define UART_LSR_BI		0x10 /* Break interrupt indicator */
#define UART_LSR_FE		0x08 /* Frame error indicator */
#define UART_LSR_PE		0x04 /* Parity error indicator */
#define UART_LSR_OE		0x02 /* Overrun error indicator */
#define UART_LSR_DR		0x01 /* Receiver data ready */
#define UART_LSR_BRK_ERROR_BITS	(UART_LSR_BI|UART_LSR_FE|UART_LSR_PE|UART_LSR_OE)

#define UART_MSR	6	/* In:  Modem Status Register */
#define UART_MSR_DCD		0x80 /* Data Carrier Detect */
#define UART_MSR_RI		0x40 /* Ring Indicator */
#define UART_MSR_DSR		0x20 /* Data Set Ready */
#define UART_MSR_CTS		0x10 /* Clear to Send */
#define UART_MSR_DDCD		0x08 /* Delta DCD */
#define UART_MSR_TERI		0x04 /* Trailing edge ring indicator */
#define UART_MSR_DDSR		0x02 /* Delta DSR */
#define UART_MSR_DCTS		0x01 /* Delta CTS */
#define UART_MSR_ANY_DELTA	(UART_MSR_DDCD|UART_MSR_TERI|UART_MSR_DDSR|UART_MSR_DCTS)

#define UART_SCR	7	/* I/O: Scratch Register */

/*
 * DLAB=1
 */
#define UART_DLL	0	/* Out: Divisor Latch Low */
#define UART_DLM	1	/* Out: Divisor Latch High */
#define UART_DIV_MAX	0xFFFF	/* Max divisor value */

/*
 * LCR=0xBF (or DLAB=1 for 16C660)
 */
#define UART_EFR	2	/* I/O: Extended Features Register */
#define UART_XR_EFR	9	/* I/O: Extended Features Register (XR17D15x) */
#define UART_EFR_CTS		0x80 /* CTS flow control */
#define UART_EFR_RTS		0x40 /* RTS flow control */
#define UART_EFR_SCD		0x20 /* Special character detect */
#define UART_EFR_ECB		0x10 /* Enhanced control bit */
/*
 * the low four bits control software flow control
 */

/*
 * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654
 */
#define UART_XON1	4	/* I/O: Xon character 1 */
#define UART_XON2	5	/* I/O: Xon character 2 */
#define UART_XOFF1	6	/* I/O: Xoff character 1 */
#define UART_XOFF2	7	/* I/O: Xoff character 2 */

/*
 * EFR[4]=1 MCR[6]=1, TI16C752
 */
#define UART_TI752_TCR	6	/* I/O: transmission control register */
#define UART_TI752_TLR	7	/* I/O: trigger level register */

/*
 * LCR=0xBF, XR16C85x
 */
#define UART_TRG	0	/* FCTR bit 7 selects Rx or Tx
				 * In: Fifo count
				 * Out: Fifo custom trigger levels */
/*
 * These are the definitions for the Programmable Trigger Register
 */
#define UART_TRG_1		0x01
#define UART_TRG_4		0x04
#define UART_TRG_8		0x08
#define UART_TRG_16		0x10
#define UART_TRG_32		0x20
#define UART_TRG_64		0x40
#define UART_TRG_96		0x60
#define UART_TRG_120		0x78
#define UART_TRG_128		0x80

#define UART_FCTR	1	/* Feature Control Register */
#define UART_FCTR_RTS_NODELAY	0x00  /* RTS flow control delay */
#define UART_FCTR_RTS_4DELAY	0x01
#define UART_FCTR_RTS_6DELAY	0x02
#define UART_FCTR_RTS_8DELAY	0x03
#define UART_FCTR_IRDA		0x04  /* IrDa data encode select */
#define UART_FCTR_TX_INT	0x08  /* Tx interrupt type select */
#define UART_FCTR_TRGA		0x00  /* Tx/Rx 550 trigger table select */
#define UART_FCTR_TRGB		0x10  /* Tx/Rx 650 trigger table select */
#define UART_FCTR_TRGC		0x20  /* Tx/Rx 654 trigger table select */
#define UART_FCTR_TRGD		0x30  /* Tx/Rx 850 programmable trigger select */
#define UART_FCTR_SCR_SWAP	0x40  /* Scratch pad register swap */
#define UART_FCTR_RX		0x00  /* Programmable trigger mode select */
#define UART_FCTR_TX		0x80  /* Programmable trigger mode select */

/*
 * LCR=0xBF, FCTR[6]=1
 */
#define UART_EMSR	7	/* Extended Mode Select Register */
#define UART_EMSR_FIFO_COUNT	0x01  /* Rx/Tx select */
#define UART_EMSR_ALT_COUNT	0x02  /* Alternating count select */

/*
 * The Intel XScale on-chip UARTs define these bits
 */
#define UART_IER_DMAE	0x80	/* DMA Requests Enable */
#define UART_IER_UUE	0x40	/* UART Unit Enable */
#define UART_IER_NRZE	0x20	/* NRZ coding Enable */
#define UART_IER_RTOIE	0x10	/* Receiver Time Out Interrupt Enable */

#define UART_IIR_TOD	0x08	/* Character Timeout Indication Detected */

#define UART_FCR_PXAR1	0x00	/* receive FIFO threshold = 1 */
#define UART_FCR_PXAR8	0x40	/* receive FIFO threshold = 8 */
#define UART_FCR_PXAR16	0x80	/* receive FIFO threshold = 16 */
#define UART_FCR_PXAR32	0xc0	/* receive FIFO threshold = 32 */

/*
 * These register definitions are for the 16C950
 */
#define UART_ASR	0x01	/* Additional Status Register */
#define UART_RFL	0x03	/* Receiver FIFO level */
#define UART_TFL 	0x04	/* Transmitter FIFO level */
#define UART_ICR	0x05	/* Index Control Register */

/* The 16950 ICR registers */
#define UART_ACR	0x00	/* Additional Control Register */
#define UART_CPR	0x01	/* Clock Prescalar Register */
#define UART_TCR	0x02	/* Times Clock Register */
#define UART_CKS	0x03	/* Clock Select Register */
#define UART_TTL	0x04	/* Transmitter Interrupt Trigger Level */
#define UART_RTL	0x05	/* Receiver Interrupt Trigger Level */
#define UART_FCL	0x06	/* Flow Control Level Lower */
#define UART_FCH	0x07	/* Flow Control Level Higher */
#define UART_ID1	0x08	/* ID #1 */
#define UART_ID2	0x09	/* ID #2 */
#define UART_ID3	0x0A	/* ID #3 */
#define UART_REV	0x0B	/* Revision */
#define UART_CSR	0x0C	/* Channel Software Reset */
#define UART_NMR	0x0D	/* Nine-bit Mode Register */
#define UART_CTR	0xFF

/*
 * The 16C950 Additional Control Register
 */
#define UART_ACR_RXDIS	0x01	/* Receiver disable */
#define UART_ACR_TXDIS	0x02	/* Transmitter disable */
#define UART_ACR_DSRFC	0x04	/* DSR Flow Control */
#define UART_ACR_TLENB	0x20	/* 950 trigger levels enable */
#define UART_ACR_ICRRD	0x40	/* ICR Read enable */
#define UART_ACR_ASREN	0x80	/* Additional status enable */

/*
 * These definitions are for the RSA-DV II/S card, from
 *
 * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
 */

#define UART_RSA_BASE (-8)

#define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */

#define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */
#define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */
#define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
#define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */

#define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */

#define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
#define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
#define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */
#define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */
#define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */

#define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */

#define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */
#define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */
#define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */
#define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */
#define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
#define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */
#define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */
#define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */

#define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */

#define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */

#define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */

#define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */

/*
 * The RSA DSV/II board has two fixed clock frequencies.  One is the
 * standard rate, and the other is 8 times faster.
 */
#define SERIAL_RSA_BAUD_BASE (921600)
#define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)

/* Extra registers for TI DA8xx/66AK2x */
#define UART_DA830_PWREMU_MGMT	12

/* PWREMU_MGMT register bits */
#define UART_DA830_PWREMU_MGMT_FREE	(1 << 0)  /* Free-running mode */
#define UART_DA830_PWREMU_MGMT_URRST	(1 << 13) /* Receiver reset/enable */
#define UART_DA830_PWREMU_MGMT_UTRST	(1 << 14) /* Transmitter reset/enable */

/*
 * Extra serial register definitions for the internal UARTs
 * in TI OMAP processors.
 */
#define OMAP1_UART1_BASE	0xfffb0000
#define OMAP1_UART2_BASE	0xfffb0800
#define OMAP1_UART3_BASE	0xfffb9800
#define UART_OMAP_MDR1		0x08	/* Mode definition register */
#define UART_OMAP_MDR2		0x09	/* Mode definition register 2 */
#define UART_OMAP_SCR		0x10	/* Supplementary control register */
#define UART_OMAP_SSR		0x11	/* Supplementary status register */
#define UART_OMAP_EBLR		0x12	/* BOF length register */
#define UART_OMAP_OSC_12M_SEL	0x13	/* OMAP1510 12MHz osc select */
#define UART_OMAP_MVER		0x14	/* Module version register */
#define UART_OMAP_SYSC		0x15	/* System configuration register */
#define UART_OMAP_SYSS		0x16	/* System status register */
#define UART_OMAP_WER		0x17	/* Wake-up enable register */
#define UART_OMAP_TX_LVL	0x1a	/* TX FIFO level register */

/*
 * These are the definitions for the MDR1 register
 */
#define UART_OMAP_MDR1_16X_MODE		0x00	/* UART 16x mode */
#define UART_OMAP_MDR1_SIR_MODE		0x01	/* SIR mode */
#define UART_OMAP_MDR1_16X_ABAUD_MODE	0x02	/* UART 16x auto-baud */
#define UART_OMAP_MDR1_13X_MODE		0x03	/* UART 13x mode */
#define UART_OMAP_MDR1_MIR_MODE		0x04	/* MIR mode */
#define UART_OMAP_MDR1_FIR_MODE		0x05	/* FIR mode */
#define UART_OMAP_MDR1_CIR_MODE		0x06	/* CIR mode */
#define UART_OMAP_MDR1_DISABLE		0x07	/* Disable (default state) */

/*
 * These are definitions for the Altera ALTR_16550_F32/F64/F128
 * Normalized from 0x100 to 0x40 because of shift by 2 (32 bit regs).
 */
#define UART_ALTR_AFR		0x40	/* Additional Features Register */
#define UART_ALTR_EN_TXFIFO_LW	0x01	/* Enable the TX FIFO Low Watermark */
#define UART_ALTR_TX_LOW	0x41	/* Tx FIFO Low Watermark */

#endif /* _LINUX_SERIAL_REG_H */